1. Field of the Invention
The present invention relates to devices used to determine the duty time and length of a digital signal. More particularly, the present invention relates to circuits used to measure the time difference between either the rising edge and falling edge or successive rise edges. The present invention provides a means for measuring that time difference with minimal processing by a host processor.
2. Description of the Prior Art
Digital computers are comprised of a variety of components designed to work together in a coordinated manner. The central processing unit, otherwise known as the microprocessor or microcontroller in small portable-type computers, is specifically designed to coordinate those various components. Such components include, but are not limited to, the Read-Only Memory (ROM), Random-Access Memory (RAM), various counters and registers, as well as interfaces for the transferral of information between the computer and external and internal systems. That information is embodied in digital signals. Those digital signals are characterized as pulses of varying duration. Given the well-known complexity associated with these systems, it is important that most computing systems include timing and related control circuitry to ensure that, among other things, the transfer of digital signals between the processor and external components remains coordinated.
While the processor is certainly the key component of any computing system designed to complete a task, timer circuitry is often necessary to coordinate activities associated with completing the task, particularly regarding the transfer of information related to external events. A generic timer of the type used in most processing systems includes a reload/counter, and a register for receiving information from the counter. The reload subcircuitry of the timer is generally used to time the transmission of data out from the processor and is only of peripheral interest in regard to the present invention.
The counter component of the timer is typically designed to count the on-going number of pulses associated with a signal of fixed frequency--generally provided by a system clock that maintains a signal of well-defined frequency. The pulses are designed to be associated with a particular event in that the number of pulses can be used to time the beginning and ending of an event. The register latches or captures the count information from the counter when requested to do so by the processor. That is, the processor enables the capture register, by sending a triggering signal related to a particular incoming signal, and thereby spurs the register to fetch from the counter the count value at that time. The triggering occurs at the outset of a triggering event or set of events--such as a rising edge associated with the initiation of an event, and then a falling edge indicating the end of the event--of an incoming signal for which a duration is to be obtained.
The duration of interest is commonly the difference between the rising edge and the falling edge of that incoming signal. It may, however, be the difference in time from a rising edge to the next successive rising edge, when the time for a complete cycle of the incoming signal is to be obtained. Defining the duration of that signal of interest enables the controller to coordinate the transfer of the information associated with that signal, or to otherwise manipulate that signal. Inaccuracy in the measurement of signal duration will of course adversely affect the transfer and/or manipulation of the associated information. One example of an event for which timing accuracy is important is a remote vehicle-speed-measurement system. The first event would be the indication that the vehicle had passed a first fixed location (the first event to be captured). The second event would be the vehicle's passing of a second fixed location (the second event to be captured). A system timer would be used to count the number of pulses between those two capture events, which count would be passed to the processor for manipulation to determine whether the vehicle had exceeded a speed limit. Of course, there are countless other examples of event timings of interest. In most such cases, it is important that the pulse count be accurate. Additionally, in order for this system to work, an initial predictable incoming event rate must be introduced such that the system clock and the frequency of the signal to be captured are aligned. That predictable value is event dependent and may be brief or extended.
In the prior-art systems, the counter, which may be a ripple or free-running counter for example, continues to count down (from FF for an 8-bit counter or from FFFF for a 16-bit counter for example) as a function of a triggering pulse associated with a rising edge of the signal from the system clock. When the capture register is triggered by the processing unit to fetch the counter value at the time of the triggering event associated with the incoming signal to be measured, the counter value at that moment is latched to the capture register. The capture register then transmits that count value to the processing unit which in turn transfers the information to RAM. The processing unit again triggers the capture register upon the occurrence of a second triggering event, either a falling edge of the incoming signal--for half-cycle-time measurement--or on the next rising edge--for full-cycle-time measurement. When that second triggering event occurs, the capture register is again enabled to fetch the count value at that time. The second count value is again transferred to RAM. The processor then performs a subtraction calculation to determine the number of cycles of the system clock that have passed during the duration of either the half cycle or full cycle of the incoming signal. That information is then used to calculate the difference between the two triggering events, or the duration of the event.
This method for obtaining event duration information has been the standard technique, although variants have been developed, apparently in order to increase time-difference measurement accuracy and consistency. In addition to one of the original ways for doing so, described in U.S. Pat. No. 4,222,103, issued to Chamberlin, a more recent technique is described by Ogita in U.S. Pat. No. 5,218,693. Unfortunately, as with all prior timing measurement systems, these particular systems require the use of valuable RAM space and valuable processor or controller processing resources in order to resolve the information twice obtained from the counter. It would be preferable if the timing component of the complete system could be used to obtain the incoming signal time difference so as to free up RAM space and to minimize processing resources of the controller. Therefore, what is needed is a timing system that includes circuitry for determining the difference between the rise and fall times, or the rise and rise times of digital signals. What is also needed is such a timing system that can be used to obtain information associated with incoming signal timing without using RAM and with minimal reliance upon a controller or processor to manipulate data to determine that difference.